Pipeline stage? 5stages, IF/ID/EX/MEM/WB
Why using pipeline? throughput
What’s the side effect of pipeline? latency, data hazard
*Well, hazard, how many kinds of hazard and how to solve?
Control hazard-instruction predicting, branch predicting.
*What to do if branch predicting failed, make incorrect predict?

Sequential logic, D flip flop
Writing verilog code: D flip flop? and D latch? First asynchronous reset then modify to synchronous reset/add enable signal
Draw circuit diagram for D flip flop with en, two ways?
Setup time? Hold time? If input signal does not meet the timing requirement what’s the output and behavior of this Dff?
*Synchronizer: a simple level sensitive synchronizer, glitch, (detail information): What’s the output of the first Dff if it is under metastable state? And what will the final output be and why the final output can be synchronized? draw clock sequence diagram, show the metastable state of first output and explain.

Memory system in microprocessor
*What is a cache? how does it work? temporal and spatial re-use principle.
Three kinds of mapping between cache and main memory? direct association, N-way set association and fully association.
*What’s the different between N-way set association and fully association?
*Given a cache of 32k in size, 32bytes line, tell me what’s the structure of this cache, how many sets and tags in the cache.
*Do you familiar with memory management unit, or TLB? (reference provided by wiki, MMU, TLB) //完全不会,需要恶补

Some topic on verification flow, your project experience and what did you do for your project, in detail.

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